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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 | /* * Copyright (c) 2007-2010 Apple Inc. All rights reserved. * * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ * * This file contains Original Code and/or Modifications of Original Code * as defined in and that are subject to the Apple Public Source License * Version 2.0 (the 'License'). You may not use this file except in * compliance with the License. The rights granted to you under the License * may not be used to create, or enable the creation or redistribution of, * unlawful or unlicensed copies of an Apple operating system, or to * circumvent, violate, or enable the circumvention or violation of, any * terms of an Apple operating system software license agreement. * * Please obtain a copy of the License at * http://www.opensource.apple.com/apsl/ and read it before using this file. * * The Original Code and all software distributed under the License are * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. * Please see the License for the specific language governing rights and * limitations under the License. * * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ */ #include <mach/machine.h> #include <mach/processor.h> #include <kern/kalloc.h> #include <i386/cpu_affinity.h> #include <i386/cpu_topology.h> #include <i386/cpu_threads.h> #include <i386/machine_cpu.h> #include <i386/bit_routines.h> #include <i386/cpu_data.h> #include <i386/lapic.h> #include <i386/machine_routines.h> #include <stddef.h> __private_extern__ void qsort( void * array, size_t nmembers, size_t member_size, int (*)(const void *, const void *)); static int lapicid_cmp(const void *x, const void *y); static x86_affinity_set_t *find_cache_affinity(x86_cpu_cache_t *L2_cachep); x86_affinity_set_t *x86_affinities = NULL; static int x86_affinity_count = 0; extern cpu_data_t cpshadows[]; #if DEVELOPMENT || DEBUG void traptrace_init(void); #endif /* DEVELOPMENT || DEBUG */ /* Re-sort double-mapped CPU data shadows after topology discovery sorts the * primary CPU data structures by physical/APIC CPU ID. */ static void cpu_shadow_sort(int ncpus) { for (int i = 0; i < ncpus; i++) { cpu_data_t *cpup = cpu_datap(i); ptrdiff_t coff = cpup - cpu_datap(0); cpup->cd_shadow = &cpshadows[coff]; } } /* * cpu_topology_sort() is called after all processors have been registered but * before any non-boot processor is started. We establish canonical logical * processor numbering - logical cpus must be contiguous, zero-based and * assigned in physical (local apic id) order. This step is required because * the discovery/registration order is non-deterministic - cores are registered * in differing orders over boots. Enforcing canonical numbering simplifies * identification of processors. */ void cpu_topology_sort(int ncpus) { int i; boolean_t istate; processor_t lprim = NULL; assert(machine_info.physical_cpu == 1); assert(machine_info.logical_cpu == 1); assert(master_cpu == 0); assert(cpu_number() == 0); assert(cpu_datap(0)->cpu_number == 0); uint32_t cpus_per_pset = 0; #if DEVELOPMENT || DEBUG PE_parse_boot_argn("cpus_per_pset", &cpus_per_pset, sizeof(cpus_per_pset)); #endif /* Lights out for this */ istate = ml_set_interrupts_enabled(FALSE); if (topo_dbg) { TOPO_DBG("cpu_topology_start() %d cpu%s registered\n", ncpus, (ncpus > 1) ? "s" : ""); for (i = 0; i < ncpus; i++) { cpu_data_t *cpup = cpu_datap(i); TOPO_DBG("\tcpu_data[%d]:%p local apic 0x%x\n", i, (void *) cpup, cpup->cpu_phys_number); } } /* * Re-order the cpu_data_ptr vector sorting by physical id. * Skip the boot processor, it's required to be correct. */ if (ncpus > 1) { qsort((void *) &cpu_data_ptr[1], ncpus - 1, sizeof(cpu_data_t *), lapicid_cmp); } if (topo_dbg) { TOPO_DBG("cpu_topology_start() after sorting:\n"); for (i = 0; i < ncpus; i++) { cpu_data_t *cpup = cpu_datap(i); TOPO_DBG("\tcpu_data[%d]:%p local apic 0x%x\n", i, (void *) cpup, cpup->cpu_phys_number); } } /* * Finalize logical numbers and map kept by the lapic code. */ for (i = 0; i < ncpus; i++) { cpu_data_t *cpup = cpu_datap(i); if (cpup->cpu_number != i) { kprintf("cpu_datap(%d):%p local apic id 0x%x " "remapped from %d\n", i, cpup, cpup->cpu_phys_number, cpup->cpu_number); } cpup->cpu_number = i; lapic_cpu_map(cpup->cpu_phys_number, i); x86_set_logical_topology(&cpup->lcpu, cpup->cpu_phys_number, i); } cpu_shadow_sort(ncpus); x86_validate_topology(); ml_set_interrupts_enabled(istate); TOPO_DBG("cpu_topology_start() LLC is L%d\n", topoParms.LLCDepth + 1); #if DEVELOPMENT || DEBUG traptrace_init(); #endif /* DEVELOPMENT || DEBUG */ /* * Let the CPU Power Management know that the topology is stable. */ topoParms.stable = TRUE; pmCPUStateInit(); /* * Iterate over all logical cpus finding or creating the affinity set * for their LLC cache. Each affinity set possesses a processor set * into which each logical processor is added. */ TOPO_DBG("cpu_topology_start() creating affinity sets:ncpus=%d max_cpus=%d\n", ncpus, machine_info.max_cpus); uint32_t pset_cluster_id = 0; for (i = 0; i < machine_info.max_cpus; i++) { cpu_data_t *cpup = cpu_datap(i); x86_lcpu_t *lcpup = cpu_to_lcpu(i); x86_cpu_cache_t *LLC_cachep; x86_affinity_set_t *aset; LLC_cachep = lcpup->caches[topoParms.LLCDepth]; assert(LLC_cachep->type == CPU_CACHE_TYPE_UNIF); aset = find_cache_affinity(LLC_cachep); if ((aset == NULL) || ((cpus_per_pset != 0) && (i % cpus_per_pset) == 0)) { aset = kalloc_type(x86_affinity_set_t, Z_WAITOK | Z_NOFAIL); aset->next = x86_affinities; x86_affinities = aset; aset->num = x86_affinity_count++; aset->cache = LLC_cachep; if (i == master_cpu) { aset->pset = processor_pset(master_processor); } else { pset_cluster_id++; aset->pset = pset_create(CLUSTER_TYPE_SMP, pset_cluster_id, pset_cluster_id); if (aset->pset == PROCESSOR_SET_NULL) { panic("cpu_topology_start: pset_create"); } } TOPO_DBG("\tnew set %p(%d) pset %p for cache %p\n", aset, aset->num, aset->pset, aset->cache); } TOPO_DBG("\tprocessor_init set %p(%d) lcpup %p(%d) cpu %p processor %p\n", aset, aset->num, lcpup, lcpup->cpu_num, cpup, cpup->cpu_processor); if (i != master_cpu) { processor_init(cpup->cpu_processor, i, aset->pset); } if (lcpup->core->num_lcpus > 1) { if (lcpup->lnum == 0) { lprim = cpup->cpu_processor; } #if CONFIG_SCHED_SMT processor_set_primary(cpup->cpu_processor, lprim); #endif /* CONFIG_SCHED_SMT */ } } if (machine_info.max_cpus < machine_info.logical_cpu_max) { /* boot-args cpus=n is set, so adjust max numbers to match */ int logical_max = machine_info.max_cpus; int physical_max = logical_max; if (machine_info.logical_cpu_max != machine_info.physical_cpu_max) { physical_max = (logical_max + 1) / 2; } machine_info.logical_cpu_max = logical_max; machine_info.physical_cpu_max = physical_max; } } /* We got a request to start a CPU. Check that this CPU is within the * max cpu limit set before we do. */ kern_return_t cpu_topology_start_cpu( int cpunum ) { int ncpus = machine_info.max_cpus; int i = cpunum; /* Decide whether to start a CPU, and actually start it */ TOPO_DBG("cpu_topology_start() processor_start():\n"); if (i < ncpus) { TOPO_DBG("\tlcpu %d\n", cpu_datap(i)->cpu_number); processor_boot(cpu_datap(i)->cpu_processor); return KERN_SUCCESS; } else { return KERN_FAILURE; } } static int lapicid_cmp(const void *x, const void *y) { cpu_data_t *cpu_x = *((cpu_data_t **)(uintptr_t)x); cpu_data_t *cpu_y = *((cpu_data_t **)(uintptr_t)y); TOPO_DBG("lapicid_cmp(%p,%p) (%d,%d)\n", x, y, cpu_x->cpu_phys_number, cpu_y->cpu_phys_number); if (cpu_x->cpu_phys_number < cpu_y->cpu_phys_number) { return -1; } if (cpu_x->cpu_phys_number == cpu_y->cpu_phys_number) { return 0; } return 1; } static x86_affinity_set_t * find_cache_affinity(x86_cpu_cache_t *l2_cachep) { x86_affinity_set_t *aset; for (aset = x86_affinities; aset != NULL; aset = aset->next) { if (l2_cachep == aset->cache) { break; } } return aset; } int ml_get_max_affinity_sets(void) { return x86_affinity_count; } processor_set_t ml_affinity_to_pset(uint32_t affinity_num) { x86_affinity_set_t *aset; for (aset = x86_affinities; aset != NULL; aset = aset->next) { if (affinity_num == aset->num) { break; } } return (aset == NULL) ? PROCESSOR_SET_NULL : aset->pset; } uint64_t ml_cpu_cache_size(unsigned int level) { x86_cpu_cache_t *cachep; if (level == 0) { return machine_info.max_mem; } else if (1 <= level && level <= MAX_CACHE_DEPTH) { cachep = current_cpu_datap()->lcpu.caches[level - 1]; return cachep ? cachep->cache_size : 0; } else { return 0; } } unsigned int ml_cpu_cache_sharing(unsigned int level, cluster_type_t cluster_type __unused, bool include_all_cpu_types __unused) { x86_cpu_cache_t *cachep; if (level == 0) { return machine_info.max_cpus; } else if (1 <= level && level <= MAX_CACHE_DEPTH) { cachep = current_cpu_datap()->lcpu.caches[level - 1]; return cachep ? cachep->nlcpus : 0; } else { return 0; } } #if DEVELOPMENT || DEBUG volatile int traptrace_enabled = 1; uint32_t traptrace_entries_per_cpu = 0; uint32_t PERCPU_DATA(traptrace_next); traptrace_entry_t *PERCPU_DATA(traptrace_ring); static void init_traptrace_bufs(int entries_per_cpu) { size_t size = entries_per_cpu * sizeof(traptrace_entry_t); percpu_foreach(ring, traptrace_ring) { *ring = zalloc_permanent_tag(size, 63, VM_KERN_MEMORY_DIAG); }; traptrace_entries_per_cpu = entries_per_cpu; } static void gentrace_configure_from_bootargs(const char *ena_prop, int *ena_valp, const char *epc_prop, int *epcp, int max_epc, int def_epc, int override) { if (kern_feature_override(override)) { *ena_valp = 0; } (void) PE_parse_boot_argn(ena_prop, ena_valp, sizeof(*ena_valp)); if (*ena_valp == 0) { return; } if (PE_parse_boot_argn(epc_prop, epcp, sizeof(*epcp)) && (*epcp < 1 || *epcp > max_epc)) { *epcp = def_epc; } } void traptrace_init(void) { int entries_per_cpu = DEFAULT_TRAPTRACE_ENTRIES_PER_CPU; int enable = traptrace_enabled; gentrace_configure_from_bootargs("traptrace", &enable, "traptrace_epc", &entries_per_cpu, TRAPTRACE_MAX_ENTRIES_PER_CPU, DEFAULT_TRAPTRACE_ENTRIES_PER_CPU, KF_TRAPTRACE_OVRD); traptrace_enabled = enable; if (traptrace_enabled) { init_traptrace_bufs(entries_per_cpu); } } #endif /* DEVELOPMENT || DEBUG */ |